DocumentCode
1978435
Title
Design QC-LDPC coder based on FPGA
Author
Meng, Mingchuan ; Guan, He ; Li, Jing
Author_Institution
Qinggong Coll., Hebei United Univ., Tangshan, China
fYear
2011
fDate
16-18 Sept. 2011
Firstpage
1520
Lastpage
1522
Abstract
In this paper we study some fundamental properties of QC-LDPC code, we use a recursive compression algorithm to optimize the structure of QC-LDPC code, it can effectively reduce the coding complexity, save the space which is used to storage QC-LDPC code, and don´t need to reduce its error correction performance. We use VHDL language to design QC-LDPC decoder in the FPGA chip. This system was simulated in Quartus 117.2.
Keywords
codecs; field programmable gate arrays; network synthesis; parity check codes; FPGA chip; QC-LDPC coder design; Quartus 117.2; VHDL language; coding complexity; recursive compression algorithm; Compression algorithms; Decoding; Educational institutions; Field programmable gate arrays; Lattices; Medical services; Parity check codes; FPGA; QC-LDPC code; recursive compression algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location
Yichang
Print_ISBN
978-1-4244-8162-0
Type
conf
DOI
10.1109/ICECENG.2011.6057306
Filename
6057306
Link To Document