From RTL to GDSII: An ASIC design course development using Synopsys® University Program

Author

Lu, Jianchao ; Taskin, Baris

Author_Institution

Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA

fYear

2011

fDate

5-6 June 2011

Firstpage

72

Lastpage

75

Abstract

The development of an ASIC design course using the Synopsys® University Program lectures, labs and tools is presented in this paper. The ASIC design course lasts for 20 weeks and the students learn the design flow using tools including Design Compiler™, IC Compiler™ and PrimeTime™. The syllabus is developed based on the Synopsys® University Program Curriculum. Besides the curriculum, the students are assigned projects to synthesize some small circuits to gain more in-depth knowledge about the ASIC design flow. A keystone project is assigned to facilitate the application of the entire IC physical design flow on an industrial size processor design.

Keywords

application specific integrated circuits; educational courses; educational institutions; electronic engineering education; integrated circuit design; ASIC design course development; GDSII; IC compiler; IC physical design flow; PrimeTime; RTL; Synopsys university program curriculum; design compiler; industrial size processor design; Application specific integrated circuits; Courseware; Libraries; Timing; Training; Tutorials; ASIC design course; Synopsys®;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education (MSE), 2011 IEEE International Conference on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4577-0548-9

Electronic_ISBN

978-1-4577-0550-2

Type

conf

DOI

10.1109/MSE.2011.5937096

Filename

5937096