Device scaling model for bulk FinFETs

FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (V_th), off-state current (I_OFF)>; drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides predicting the effects of technology scaling, this model provides good insight in terms of device design. By accounting for the effects of fin geometry variation and the drain voltage (V_d) on the effective fin doping (N_a(ef)), the present work is very useful in determining N_a(ff)) for low V_th, standard V_th and high V_th applications. Based on this model, it is also possible to determine the geometrical parameters required to achieve SS = 80 mV/dec, DIBL = 50 mV/V.