FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

Author

Sklénard, B. ; Xu, C. ; Batude, P. ; Previtali, B. ; Tabone, C. ; Rafhay, Q. ; Colombeau, B. ; Khaja, F.-A. ; Martín-Bragado, I. ; Berthoz, J. ; Allain, F. ; Toffoli, A. ; Kies, R. ; Jaud, M.-A. ; Rivallin, P. ; Cristoloveanu, S. ; Tavernier, C. ; Faynot,

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

6-7 March 2012

Firstpage

169

Lastpage

172

Abstract

In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.

Keywords

MOSFET; Monte Carlo methods; elemental semiconductors; leakage currents; silicon; silicon-on-insulator; FDSOI device; KMC simulation; MOSFET; Si; channel thickness reduction; fully-depleted SOI device; kinetic Monte Carlo simulation; leakage current; low junction leakage reduction; low temperature processing; size 6 nm; Annealing; Films; Implants; Junctions; Logic gates; Silicon; Silicon on insulator technology; 3D sequential integration; EOR defects; Fully-depleted SOI (FDSOI); SPE; low temperature processes;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4673-0191-6

Electronic_ISBN

978-1-4673-0190-9

Type

conf

DOI

10.1109/ULIS.2012.6193384

Filename

6193384