DocumentCode
1979083
Title
A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-order noise-shaping TDC and a transformer-coupled QVCO
Author
Ng, Alan W L ; Zheng, Shiyuan ; Luong, Howard C.
Author_Institution
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
fYear
2012
fDate
17-21 Sept. 2012
Firstpage
189
Lastpage
192
Abstract
A 4.1GHz-6.5GHz all-digital fractional-n frequency synthesizer is presented employing a 2nd-order noise-shaping time-to-digital converter (TDC) and an embedded-FIR-filter transformer-coupled quadrature digitally-control oscillator (QDCO). Implemented in a 65nm CMOS, the prototype measures phase noise of -100dBc/Hz in-band and -145dBc/Hz at 20MHz offset from a 4.5GHz carrier while consuming 26mW from 1.2V supply and occupying 1mm2. The IQ phase error is smaller than 1.2°
Keywords
CMOS integrated circuits; FIR filters; frequency synthesizers; oscillators; phase noise; time-digital conversion; 2nd-order noise-shaping TDC; 2nd-order noise-shaping time-to-digital converter; CMOS; IQ phase error; QDCO; all-digital fractional-n frequency synthesizer; embedded-FIR-filter; frequency 20 MHz; frequency 4.1 GHz to 6.5 GHz; phase noise measurement; power 26 mW; size 65 nm; transformer-coupled QVCO; transformer-coupled quadrature digitally-control oscillator; voltage 1.2 V; Delay; Digital filters; Noise shaping; Phase locked loops; Phase noise; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location
Bordeaux
ISSN
1930-8833
Print_ISBN
978-1-4673-2212-6
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2012.6341290
Filename
6341290
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