A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC

In this paper, a 3mW 0.004mm² 6-bit time-to-digital converter (TDC) is presented. By re-using a single delay cell and sampling flip-flop (FF), mismatch free operation is achieved. PVT variations are tracked and corrected by a digital frequency lock loop (DFLL). The proposed TDC is demonstrated in a digital fractional-N PLL for WiFi/4G radios. A 20-bit high dynamic range (DR) digital-to-analog converter (DAC) drives the VCO to achieve 100Hz resolution. The PLL is fabricated in 32nm digital SoC CMOS with a flip-chip BGA package. The PLL produces a 2.5GHz band LO output with -35dBc integrated phase noise (10kHz to 10MHz) and the worst case spur less than -50dBc while consuming 21mW.