State of the art low power (42 mW per flip-flop) 150 GHz+ CML static divider implemented in scaled 0.2 m emitter-width InP DHBTs

Recent development efforts in scaling InP DHBT technologies have pushed transistor cutoff frequencies beyond 400 GHz and demonstrated static flip-flop circuits clocking in excess of 150 GHz. Despite the impressive clock rates, obtaining these operating speeds has required an increase in collector current densities that has largely offset the power reductions achieved to date in scaling the emitter area of the devices in these technologies. Further lateral scaling is required to manage thermal concerns and enable logic circuits of greater complexity. Measured results are shown of a static frequency divider realized in a 0.2 m InP/InGaAs/InP DHBT technology that lowers flip-flop power dissipation to 42 mW while clocking at 150 GHz rates. This represents a factor of two improvement in the state of the art power-delay product over previously reported logic circuits operating at >120 GHz clock rates