Title :
A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4
Author :
Li, Dan ; Minoia, Gabriele ; Repossi, Matteo ; Baldi, Daniele ; Temporiti, Enrico ; Mazzanti, Andrea ; Svelto, Francesco
Author_Institution :
Dipt. di Ing. Ind. e dell´´ Inf., Univ. di Pavia, Pavia, Italy
Abstract :
Shunt-feedback TIAs suffer from a trade-off between noise and bandwidth. In this work we propose a two stage 25Gb/s front-end, made of a low noise narrow-band TIA followed by an equalizer aimed at restoring the required bandwidth, providing a 4x noise power reduction compared to a traditional design approach. A 65nm receiver cascading the proposed front-end, the limiting amplifier and a buffer, tailored to 100GBASE-LR4, demonstrates a gain of 83dBΩ, an input referred equivalent rms noise current of 2.44μA and an electrical analog bandwidth tunable between 10.6GHz and 18.2GHz. The power consumption is 93mW with a FOM of 2066GHz·Ω/mW.
Keywords :
CMOS integrated circuits; buffer circuits; equalisers; integrated circuit noise; mean square error methods; operational amplifiers; optical receivers; power consumption; bandwidth 10 GHz to 18.2 GHz; bit rate 25 Gbit/s; buffer; current 2.44 muA; electrical analog bandwidth; equalizer; equivalent rms noise current; limiting amplifier; low noise CMOS receiver; low noise narrow-band TIA; noise power reduction; power 93 mW; power consumption; shunt-feedback; size 65 nm; trade-off; two stage front-end; Bandwidth; CMOS integrated circuits; Equalizers; Noise; Optical fiber amplifiers; Radio frequency; Receivers;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341298
