Title :
A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching
Author :
Seth, Sumantra ; Wadekar, Jayesh
Author_Institution :
Texas Instrum., India
Abstract :
A self biased cross coupled 12Mbps 3.3V differential voltage driver presented with <;+/-3% rise-fall time mismatch for paired transitions ensuring accurate cross over voltage. Implemented in 45nm CMOS technology without 3.3V gate oxide device, design occupies 0.083 mm2 and consumes <; 15mW for 50pF load with 6MHz clock pattern. This architecture achieves a ~1.57X rise-fall time variation over 12X load capacitor variation across process, voltage and temperature.
Keywords :
CMOS integrated circuits; driver circuits; CMOS technology; bit rate 12 Mbit/s; cross-over matching; differential self-biased slew rate controlled driver; differential voltage driver; load capacitor variation; rise-fall time matching; size 45 nm; voltage 3.3 V; Capacitors; Clamps; Integrated circuits; Logic gates; Silicon; Transistors; Voltage control;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341300
