Title :
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations
Author :
Yamamoto, Yasue ; Kawasumi, Atsushi ; Moriwaki, Shinichi ; Suzuki, Toshikazu ; Miyano, Shinji ; Shinohara, Hirofumi
Author_Institution :
Extremely Low Power Lab., Semicond. Technol. Acad. Res. Center (STARC), Tokyo, Japan
Abstract :
An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology.
Keywords :
CMOS memory circuits; SRAM chips; limiters; ASB scheme; BAL; BL amplitude limiter; CMOS technology; auto selective boost; cycle time acceleration; energy reduction; leakage energy dissipation; random variation; size 40 nm; slow SRAM memory cell; storage capacity 32 Kbit; voltage 0.5 V; CMOS integrated circuits; CMOS technology; Delay; Detectors; Energy dissipation; Energy measurement; Random access memory;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341318
