Layer Transfer of FDSOI CMOS to 150mm InP Substrates for Mixed-Material Integration

A low-temperature wafer bonding process has been developed to extend a silicon 3D circuit integration process to mixed-material systems. As part of this effort a functional FDSOI CMOS layer was transferred to a 150 mm diameter InP wafer without significantly affecting circuit operation. InGaAs and InGaAsP layers grown in a commercial OMVPE reactor had excellent characteristics for both 150 mm and 50 mm diameter substrates. These results suggest that it is feasible to build a near-IR imager with a tight pixel pitch by transferring a readout layer fabricated in SOI to an InGaAs/InP detector wafer