Layer Transfer of FDSOI CMOS to 150mm InP Substrates for Mixed-Material Integration

Author

Warner, K. ; Oakley, D. ; Donnelly, J. ; Keast, C. ; Shaver, D.

Author_Institution

MIT, Lexington, MA

fYear

0

fDate

0-0 0

Firstpage

226

Lastpage

228

Abstract

A low-temperature wafer bonding process has been developed to extend a silicon 3D circuit integration process to mixed-material systems. As part of this effort a functional FDSOI CMOS layer was transferred to a 150 mm diameter InP wafer without significantly affecting circuit operation. InGaAs and InGaAsP layers grown in a commercial OMVPE reactor had excellent characteristics for both 150 mm and 50 mm diameter substrates. These results suggest that it is feasible to build a near-IR imager with a tight pixel pitch by transferring a readout layer fabricated in SOI to an InGaAs/InP detector wafer

Keywords

CMOS integrated circuits; III-V semiconductors; elemental semiconductors; gallium arsenide; indium compounds; semiconductor growth; silicon; silicon-on-insulator; wafer bonding; FDSOI CMOS; InGaAs; InGaAs/InP detector wafer; InGaAsP; InP; InP substrates; OMVPE reactor; layer transfer; mixed-material integration; silicon 3D circuit integration; wafer bonding; Circuits; Detectors; Indium gallium arsenide; Indium phosphide; Laboratories; Silicon compounds; Silicon on insulator technology; Substrates; Temperature; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Indium Phosphide and Related Materials Conference Proceedings, 2006 International Conference on

Conference_Location

Princeton, NJ

Print_ISBN

0-7803-9558-1

Type

conf

DOI

10.1109/ICIPRM.2006.1634155

Filename

1634155