A digital implementation of self-organizing maps

Author

Pino, B. ; Pelayo, F.J. ; Prieto, A.

Author_Institution

Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain

fYear

1994

fDate

26-28 Sep 1994

Firstpage

260

Lastpage

267

Abstract

A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied silicon area. Several chips can be interconnected to expand the number of neurons in the network. The number of inputs per neuron depends on the internal weight memory size. The dimensionality of the network the neighbourhood topology and the rate at which the neighbouring cells learn, are programmable. The design was realised using the cells of the ES2 ecpd10 Library and simulated with Verilog. The estimated operation speed is 0.7 MCUPS/mm² during the learning phase, and 1.95 MCPS/mm² during the recall phase

Keywords

digital integrated circuits; neural chips; self-organising feature maps; 8 bit; ES2 ecpd10 Library; Verilog; bit-serial processing; digital implementation; internal weight memory size; neighbourhood topology; self-organizing maps; silicon area minimization; Artificial neural networks; Computational modeling; Computer simulation; Extraterrestrial measurements; Hardware design languages; Libraries; Network topology; Neurons; Self organizing feature maps; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on

Conference_Location

Turin

Print_ISBN

0-8186-6710-9

Type

conf

DOI

10.1109/ICMNN.1994.593718

Filename

593718