A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface

A fast locking 3.0 Gb/s clock data recovery circuit (CDR) based on the digital DLL is proposed for intra-panel clock-embedded display interface. The CDR uses 3-level sub-ranging delay control in digital DLL. Overlapping range selection, successive approximation, and highly-linear timing amplifier are used for most, intermediate, and least significant bits of control, respectively to improve both jitter immunity and dynamic range of digital DLL. The designed chip occupies 0.076 mm² active area in 0.13μm CMOS technology and consumes 6.72 mW at 3.0 Gb/s from a 1.2 V supply. The rms and pk-to-pk jitters of the recovered clock are as small as 4.8 ps and 30.8 ps, respectively.