Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency

This paper presents a variation-resilient, complete design strategy for sub-threshold Digital Signal Processors (DSP) based on a novel combination of circuit and microarchitectural techniques of which a new differential Transmission Gate logic family is the most prominent. The strategy is successfully validated by a 16bit, 90nm CMOS Multiply-Accumulate (MAC) unit which operates down to a supply of 150 mV at a clock frequency of 5MHz and 0.96 pJ energy consumption per operation. Minimum energy per operation of 0.87 pJ occurs at a supply of 190mV and a 10MHz clock.