DocumentCode
1980938
Title
Secure scan design with Isomorphic registers
Author
Banerjee, S. ; Sahana, T.
Author_Institution
Dept. of Comput. Sci. & Eng., Heritage Inst. of Technol., Kolkata, India
fYear
2011
fDate
14-15 Nov. 2011
Firstpage
62
Lastpage
66
Abstract
In this paper, we first introduce Isomorphic Redundancy concept. Two functionally equivalent shift registers can be Isomorphic to each other. They can be equivalent to each other by simple permutation of states m state tables. Two Isomorphically redundant circuits can be used to prevent two bit change insertion attack. In, addition we also propose a new model with the help of functionally equivalent shift registers. It is highly non-linear and scan-secure model.
Keywords
design for testability; shift registers; equivalent shift registers; isomorphic redundancy concept; isomorphic registers; secure scan design; 8X1 MUX; Equivalence; Extended de Bruijn graphs; Functionally equivalent; Isomorphism; LF2SR; LFSR; Shift registers; Testability;
fLanguage
English
Publisher
iet
Conference_Titel
Advances in Recent Technologies in Communication and Computing (ARTCom 2011), 3rd International Conference on
Conference_Location
Bangalore
Type
conf
DOI
10.1049/ic.2011.0052
Filename
6193541
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