An 8bit 0.35–0.8V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

Author

Yoshioka, Kentaro ; Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki

Author_Institution

Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan

fYear

2012

fDate

17-21 Sept. 2012

Firstpage

381

Lastpage

384

Abstract

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple V_cm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

Keywords

CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; comparators (circuits); low-power electronics; CMOS; asynchronous SAR ADC; biased current sources; comparator threshold; power supply variation; size 40 nm; supply voltage; voltage 0.35 V to 0.8 V; wide range dynamic threshold configuring comparator; wide range threshold configuring comparator; word length 8 bit; CMOS integrated circuits; Capacitors; Clocks; Low voltage; Power supplies; Prototypes; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2012 Proceedings of the

Conference_Location

Bordeaux

ISSN

1930-8833

Print_ISBN

978-1-4673-2212-6

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2012.6341365

Filename

6341365