Design and ASIC implementation of 2-D DWT IDWT

In this paper, high-efficient lifting-based architectures for the 5/3 discrete wavelet transform (DWT) are proposed. Filter coefficients of the biorthogonal 5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using less shifts and additions. The digital signal represented in time-scale obtained by using digital filtering techniques is known as Discrete Wavelet Transform. Here the signal to be analyzed is passed through filters with different cutoff frequencies at different scales. The DWT is computed by successive lowpass and highpass filtering of the discrete time-domain signal. The efficient architecture had been chosen for lifting scheme based DWT/IDWT process and modeled in Verilog with synthesis point of view. To meet the standards of quality, ICs should be thoroughly tested, where the necessity of suitable DFT scans arises. The estimated dynamic power consumption is 2.81mW and leakage power is 20.370uW.