Study of FPGA Implementations of Scheduling Algorithms for High-Performance Switches

One of the most important issues in current high-performance packet switches is the availability of efficient algorithms to maximize instantaneous throughput. (D)PHM and iSLIP are well-known algorithms for virtual output-queued switches. In this paper, a comparative study of the implementation of both types of schedulers in different families of FPGAs is presented. Experimental results show that, in addition to the well known advantages of using field-programmable logic, the proposed implementations provide a performance-complexity trade-off which makes them a suitable practical alternative for high-performance scheduling tasks.