Energy-efficient high-speed CMOS pipelined multiplier

This work presents the design and fabrication of an energy-efficient high-speed 8times8-bits CMOS pipelined multiplier, based on a full adder cell built with an alternative internal logic structure and a swing-restored complementary pass-transistor logic style, that reduce static power dissipation while retaining a complete voltage swing at internal nodes. Post-layout simulations show that this multiplier is able to operate up to 1.2 GHz when supplied with 3.3 V, and the power savings obtained when compared against similar pipelined multipliers are about 20% when operating with transitioning input data, 25% with non-transitioning input data and 80% with the clock signal disabled. A test chip containing the multiplier was fabricated in a 0.35 mum CMOS technology and the experimental measurements confirm its operation at 1.2 GHz with a power consumption of 180 mW for a supply voltage of 3.3 V.