Issues in the test of artificial neural networks

Test concepts for artificial neural networks are discussed. It is shown that the traditional design-for-test techniques such as (boundary) scan are of limited use owing to the high connectivity and redundancy of neural networks. An information-theoretical approach that allows for wafer as well as chip test is outlined. This approach involves testing directly on the macro properties of the neural network. The influence of device faults and built-in fault tolerance of the network is captured in so-called fault tolerant curves. These curves, obtained by simulation, link the various macro and micro properties together and allow an information-driven test of the neural network