Title :
The design of five-stage pipeline CPU based on MIPS
Author :
Ma, Hui ; Wang, Dinglei
Author_Institution :
Sch. of Comput. & Inf. Eng., Anyang Normal Univ., Anyang, China
Abstract :
Pipeline is one of the basic techniques to improve the CPU´s performance. This paper based on MIPS instruction set, designed a five-stage pipeline CPU. The CPU was implemented with schematic and VHDL language, and verified the CPU core is correct and effective in Quartus II environment.
Keywords :
hardware description languages; multiprocessing systems; pipeline processing; reduced instruction set computing; CPU core; MIPS instruction set; Quartus II environment; VHDL language; five-stage pipeline CPU; Computer architecture; Computers; Educational institutions; Hardware; Pipelines; Presses; Reduced instruction set computing; MIPS; VHDL; cpu; pipeline;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2011 International Conference on
Conference_Location :
Yichang
Print_ISBN :
978-1-4244-8162-0
DOI :
10.1109/ICECENG.2011.6057467
