TOP: an algorithm for three-level optimization of PLDs

Author

Dubrova, E. ; Ellervee, P. ; Miller, D.M. ; Muzio, J.C.

Author_Institution

Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden

fYear

2000

fDate

2000

Firstpage

751

Abstract

Summary form only given. Presents an heuristic algorithm TOP (Three-level Optimization of PLDs), targeting a three-level logic expression of type g₁ o g₂, where g₁ and g₂ are sum-of-products and “o” is a binary operation. Such an expression can be implemented by a three-level Programmable Logic Device (PLD) consisting of PLA 1 and PLA2, implementing the first two levels of logic, and a set of two-input logic expanders, implementing the third level. Each logic expander can be programmed to realize any function of two variables. PLDs of this type seem to give a good trade-off between the speed of a flat PLA and density of a multi-level network of PLAs. TOP chooses the functionality of the logic expanders so that the area of the PLAs is minimized

Keywords

Boolean functions; circuit CAD; circuit optimisation; logic CAD; minimisation of switching nets; multivalued logic circuits; programmable logic devices; PLDs; TOP; binary operation; functionality; logic expanders; multi-level network; sum-of-products; three-level logic expression; three-level optimization; two-input logic expanders; Algorithm design and analysis; Boolean functions; Circuit synthesis; Computer science; Costs; Heuristic algorithms; Logic devices; Minimization methods; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

Conference_Location

Paris

Print_ISBN

0-7695-0537-6

Type

conf

DOI

10.1109/DATE.2000.840884

Filename

840884