Design and FPGA Verification of UHF RFID reader digital baseband

The digital baseband part is the core of UHF RFID reader, its functions and features make direct impact on the reader´s performance. So this paper presents the design and FPGA Verification of digital baseband system for UHF RFID reader based on ISO 18000-6b protocol. The digital baseband system consists of two parts: transmitter and receiver, which including frame header processing module, Manchester encoding module, FMO decoding module, CRC16 check module, control module, data processing module, anti-collision module. It is described in verilog HDL in RTL level, and simulated by Modelsim with the use of testbench, with Synplify for synthesizing and Quartus II for function simulation. FPGA proved it can work properly in the specified clock frequency based on the protocol.