DocumentCode
1982878
Title
Digital design vercation based on P-stable semantics
Author
Zepeda, Claudia ; Marcial-Romero, J. Raymundo ; Osorio, Mauricio ; Castillo, Hilda ; Quintos, Daniel ; Arzola, Sergio
Author_Institution
Benemerita Univ. Autonoma de Puebla, Puebla, Mexico
fYear
2010
fDate
22-24 Feb. 2010
Firstpage
212
Lastpage
216
Abstract
We propose a framework for digital design verification based on symbolic model checking. This framework is an approach based on a novel semantics called p-stable. Additionally, we sketch how the proposed approach can be applied to verify a hardware circuit property.
Keywords
formal verification; logic programming; P-stable semantics; digital design verification; hardware circuit property; symbolic model checking; Application software; Automata; Digital circuits; Hardware; Java; Logic; Mathematical model; Process design; Prototypes; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Computer (CONIELECOMP), 2010 20th International Conference on
Conference_Location
Cholula
Print_ISBN
978-1-4244-5352-8
Electronic_ISBN
978-1-4244-5353-5
Type
conf
DOI
10.1109/CONIELECOMP.2010.5440767
Filename
5440767
Link To Document