DocumentCode
1983037
Title
Real Time Iris Segmentation on FPGA
Author
Ngo, Hau ; Shafer, Jennifer ; Ives, Robert ; Rakvic, Ryan ; Broussard, Randy
Author_Institution
Electr. & Comput. Eng. Dept., United States Naval Acad. Annapolis, Annapolis, MD, USA
fYear
2012
fDate
9-11 July 2012
Firstpage
1
Lastpage
7
Abstract
In this paper, a real time FPGA-based iris segmentation system is presented. The segmentation method implements the Canny edge detection algorithm and a circle search to detect an iris in an image or video frame. The proposed high performance architecture utilizes on-chip memory to significantly improve the throughput of the pipelined and parallel structure. A data forwarding technique is incorporated in the design to efficiently utilize the FPGA´s embedded resources. The proposed architecture demonstrates a high speed processing capability that will facilitate the use of dedicated hardware to support an iris recognition application for large databases.
Keywords
edge detection; field programmable gate arrays; iris recognition; video signal processing; Canny edge detection algorithm; FPGA; circle search; data forwarding technique; high performance architecture; image frame; iris detection; iris recognition; large database; on-chip memory; parallel structure; pipelined structure; real time iris segmentation; video frame; Clocks; Computer architecture; Field programmable gate arrays; Image edge detection; Iris recognition; Kernel; Real-time systems; Canny edge detection; FPGA-based real time processing; iris recognition; iris segmentation; on-chip buffering; pipeline and parallel architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on
Conference_Location
Delft
ISSN
2160-0511
Print_ISBN
978-1-4673-2243-0
Electronic_ISBN
2160-0511
Type
conf
DOI
10.1109/ASAP.2012.26
Filename
6341447
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