Research and Design of Plug-Type IP Information Monitoring Equipment Based on Parallel Algorithm

Author

Zhang Hui-min ; Yi, Chai ; Zeng Xiao-hong

Author_Institution

Coll. of Electron. Eng., Dept. of Commun., Chongqing Univ., Chong Qing, China

fYear

2010

fDate

20-22 Aug. 2010

Firstpage

1

Lastpage

4

Abstract

This paper presents a research and design method of plug-type IP information monitoring equipment based on parallel algorithm. It mainly uses the Ethernet hub and field-programmable gate array (FPGA) technology to implement the detection and management of full-duplex IP datagram. Meanwhile using time interval as a judge to analyze and process IP datagram. By detecting, the device can meet the design requirements, with the characteristic of real-time, not to delay the network speed, not take up IP addresses, and low cost.

Keywords

IP networks; Internet; field programmable gate arrays; local area networks; logic design; packet switching; parallel algorithms; Ethernet hub; field programmable gate array technology; full duplex IP datagram detection; full duplex IP datagram management; parallel algorithm; plug-type IP information monitoring equipment; real-time characteristic; time interval; Computers; Educational institutions; Field programmable gate arrays; Hardware design languages; IP networks; Monitoring; Parallel algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Internet Technology and Applications, 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-5142-5

Electronic_ISBN

978-1-4244-5143-2

Type

conf

DOI

10.1109/ITAPP.2010.5566563

Filename

5566563