Title :
A Linear Algebra Core Design for Efficient Level-3 BLAS
Author :
Pedram, Ardavan ; Gilani, Syed Zohaib ; Kim, Nam Sung ; Van De Geijn, Robert ; Schulte, Michael ; Gerstlauer, Andreas
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
Reducing power consumption and increasing efficiency is a key concern for many applications. It is well-accepted that specialization and heterogeneity are crucial strategies to improve both power and performance. Yet, how to design highly efficient processing elements while maintaining enough flexibility within a domain of applications is a fundamental question. In this paper, we present the design of a specialized Linear Algebra Core (LAC) for an important class of computational kernels, the level-3 Basic Linear Algebra Subprograms (BLAS). We demonstrate a detailed algorithm/architecture co-design for mapping a number of level-3 BLAS operations onto the LAC. Results show that our prototype LAC achieves a performance of around 64 GFLOPS (double precision) for these operations, while consuming less than 1.3 Watts in standard 45nm CMOS technology. This is on par with a full-custom design and up to 50× and 10× better in terms of power efficiency than CPUs and GPUs.
Keywords :
CMOS integrated circuits; computer architecture; design; general purpose computers; linear algebra; power consumption; CMOS technology; GFLOPS; basic linear algebra subprograms; computational kernels; level-3 BLAS; linear algebra core design; power consumption; Algorithm design and analysis; Bandwidth; Computer architecture; Computers; Linear algebra; Power demand; Registers; BLAS; Co-design; Linear Algebra; Low Power;
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2012 IEEE 23rd International Conference on
Conference_Location :
Delft
Print_ISBN :
978-1-4673-2243-0
Electronic_ISBN :
2160-0511
DOI :
10.1109/ASAP.2012.18