DocumentCode :
1984389
Title :
A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies
Author :
Liu, Miao ; Mak, Pui-In ; Yan, Zushu ; Martins, R.P.
Author_Institution :
State Key Lab. of Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
33
Lastpage :
36
Abstract :
This paper describes a high-voltage-enabling circuit technique for enhancing the gain precision and linearity of OpAmp-based analog circuits. Without resorting from specialized devices, a 2xVDD-enabled recycling folded cascode (RFC) OpAmp optimized in IV GP 65-nm CMOS achieves, when compared with its 1xVDD counterpart, 25-dB higher open-loop DC gain and 30-dB higher IM3 (in closed loop), under a similar power budget. These joint improvements save the need of a 2nd stage in the OpAmp when high precision and high linearity are the priorities. A voltage-conscious bias scheme and gate-drain-source engineering ensure that all devices are consistently operated within the reliability limits.
Keywords :
CMOS analogue integrated circuits; operational amplifiers; power integrated circuits; IM3; gate-drain-source engineering; high-voltage-enabled recycling folded cascode opamp-based analog circuit; nanoscale GP CMOS technology; open-loop DC gain; power budget; size 65 nm; voltage 1 V; voltage-conscious bias scheme; CMOS integrated circuits; Gain; Integrated circuit reliability; Logic gates; MOS devices; Reliability engineering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937494
Filename :
5937494
Link To Document :
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