Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique

Design optimization methodology of an output capacitor-less low-dropout regulator with small internal compensation capacitance for on-chip application with slew-rate enhancement circuit is presented in this paper. The on-chip compensation capacitance is reduced down to 1.5pF. The idea has been modeled and fabricated in a standard 0.35μm CMOS process. From experimental results, with minimum dropout voltage of 0.2V and 30μA quiescent current, the regulator implemented can operate with supply voltage from 2.4V to 3.3V at maximum loading current of 100mA.