Title :
Optimizing method of C compiler for TRON architecture
Author :
Hayashida, Seiji ; Tamaru, Kiichiro
Author_Institution :
Dept. of Adv. Microprocessor Technol., Toshiba Corp., Kawasaki, Japan
Abstract :
A description is given of the optimizing methods used in the ANSI-C compiler for the chip based on the TRON architecture. This C compiler is designed for the TLCS-90000/TX series microprocessors. For the C compiler, unique optimizing methods for the TRON architecture are used in the routines for optimization of intermediate language and code generation, in addition to the traditional global optimizing methods, such as copy propagation, loop optimization and register calling convention. Thus the compiling performance was improved. The unique features of the TRON architecture are: chained addressing mode, and the ACB and SSTR instructions. Finally, the performance of the optimizing compiler is evaluated in the terms of the execution time and object code size
Keywords :
C language; computer architecture; microprocessor chips; program compilers; standards; ACB; ANSI-C compiler; SSTR instructions; TLCS-90000/TX series microprocessors; TRON architecture; chained addressing mode; code generation; compiling performance; copy propagation; execution time; intermediate language; loop optimization; object code size; optimizing methods; register calling convention; traditional global optimizing methods; unique optimizing methods; ANSI standards; Assembly; ISO standards; Laboratories; Microprocessors; Optimization methods; Optimizing compilers; Program processors; Registers; Semiconductor devices;
Conference_Titel :
TRON Project Symposium, 1992. Proceedings., Ninth
Conference_Location :
Tokyo
Print_ISBN :
0-8186-2990-8
DOI :
10.1109/TRON.1992.313266
