DocumentCode :
1984859
Title :
TRON-specification CHIP compatibility validation
Author :
Inoue, Satoshi ; Matsui, Shigezumi ; Suzuki, Masato
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fYear :
1992
fDate :
2-4 Dec 1992
Firstpage :
47
Lastpage :
55
Abstract :
The CHIP validation suite, a set of programs for confirming whether a CHIP implementation conforms to the TRON specifications or not, was completed. The validation suite applies to specification level ≪L1R≫, and tests functions of the instruction set, addressing modes, flags and exceptions, etc. These programs were made with a specially developed tool that automatically generates assembler source codes. The size of the validation suite is nearly three million steps. The authors also developed a validation environment system such as a monitor program allowing the validation suite to be run on a tested chip
Keywords :
VLSI; formal specification; formal verification; microprocessor chips; performance evaluation; CHIP implementation; CHIP validation suite; TRON specifications; addressing modes; assembler source codes; instruction set; specification level; validation environment system; Assembly; Computer architecture; Heart; Microprocessors; Monitoring; Performance evaluation; Software testing; System testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TRON Project Symposium, 1992. Proceedings., Ninth
Conference_Location :
Tokyo
ISSN :
1063-6749
Print_ISBN :
0-8186-2990-8
Type :
conf
DOI :
10.1109/TRON.1992.313269
Filename :
313269
Link To Document :
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