Design of high-speed clock recovery circuit for burst-mode applications

This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog style clock recovery circuits. The proposed circuit recovers output clock for every transition of input data and does not accumulate output jitter. It does not require any special exquisite techniques to detect the clock with appropriate phase. The phase shifts in recovered clock for input data skew are within ±40ps. The peak to-peak jitter is 49ps and RMS jitter is 4.5ps. The cycle-to-cycle jitter tolerance is ±33.3% UI. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for a pseudo random bit sequence of 2 -1 data at 2.56Gb/s. The acquisition time for the proposed circuit is fast enough to be used in burst-mode applications such as GPON.