LFSR based deterministic hardware for at-speed BIST

Author

Vasudevan, B. ; Ross, D.E. ; Gala, M. ; Watson, K.L.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1993

fDate

6-8 April 1993

Firstpage

201

Lastpage

207

Abstract

A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.<>

Keywords

built-in self test; fault location; logic arrays; logic testing; shift registers; C-testable ILAs; LFSR; at-speed BIST; deterministic hardware; deterministic test pattern generator; linear feedback shift registers; multiple combinational faults; response analyzers; zero aliasing probability; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Read only memory; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-8186-3830-3

Type

conf

DOI

10.1109/VTEST.1993.313323

Filename

313323