• DocumentCode
    1985657
  • Title

    Signal probability calculations using partial functional manipulation

  • Author

    Kodavarti, R. ; Ross, D.E.

  • Author_Institution
    Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
  • fYear
    1993
  • fDate
    6-8 April 1993
  • Firstpage
    194
  • Lastpage
    200
  • Abstract
    Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.<>
  • Keywords
    VLSI; combinatorial circuits; integrated logic circuits; logic testing; probability; ISCAS combinational circuits; digital logic networks; linear feedback shift registers; logic circuits; partial functional manipulation; random pattern testability; signal probabilities; syndrome analysis; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Educational institutions; Fault detection; Logic testing; Probability; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
  • Conference_Location
    Atlantic City, NJ, USA
  • Print_ISBN
    0-8186-3830-3
  • Type

    conf

  • DOI
    10.1109/VTEST.1993.313324
  • Filename
    313324