DocumentCode
1985714
Title
Testability of one dimensional ILAs under multiple faults
Author
Gala, Murali M R ; Watson, Karan L. ; Ross, Don E.
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear
1993
fDate
6-8 April 1993
Firstpage
178
Lastpage
181
Abstract
Testing of one dimensional unilateral iterative logic arrays (ILAs) of combinational cells under multiple faults is discussed. It has been shown that it is possible to generate a test set for ILAs with primary outputs under multiple faults. Some ILAs have a constant number of test vectors independent of the size of the array. These types of arrays are called C-testable arrays. Present work proves that all useful one dimensional unilateral ILAs with only boundary outputs are not C-testable under multiple faults.<>
Keywords
combinatorial circuits; fault location; logic arrays; logic testing; C-testable arrays; boundary outputs; combinational cells; multiple faults; one dimensional ILAs; primary outputs; test vectors; Circuit faults; Circuit testing; Equations; Fault location; Logic testing; Sufficient conditions; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313327
Filename
313327
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