DocumentCode
1985747
Title
ECC design of a custom DRAM storage unit
Author
Peter, J.-L.
fYear
1993
fDate
6-8 April 1993
Firstpage
171
Lastpage
173
Abstract
The architecture and ECC (error correction code) implementation of a custom storage unit built with 4 Mb DRAMs packaged on 4 MB SIMM (single in line module) and controlled with a CMOS 1 micron ASIC chips set will be described. The upgrade with 16 Mb DRAMs chips packaged on 16 MB SIMM is also supported. The storage unit is designed to interface with an INTEL i486 microprocessor running at 25 MHz and to provide an optimum correction capability of the ECC based on expected DRAMs chip failures mechanisms. This storage unit is used in the 3746 model 900 Communication Controller announced by IBM. The maximum DRAM space supported is 50 SIMMs.<>
Keywords
DRAM chips; error correction codes; semiconductor storage; 3746 model 900 Communication Controller; 4 to 16 Mbits; ASIC; CMOS chip set; DRAM space; DRAMs; INTEL i486; SIMM; chip failures mechanisms; custom DRAM storage unit; optimum correction capability; Application specific integrated circuits; CMOS process; Communication system control; Control systems; Error correction codes; Failure analysis; Laboratories; Microprocessors; Packaging; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313329
Filename
313329
Link To Document