Quad DCVS: a dynamic differential logic family with precharge low and high I/O

Author

Adams, R. Dean ; Cooley, Edmond S. ; Hansen, Patrick R.

Author_Institution

Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA

fYear

1998

fDate

2-4 Mar 1998

Firstpage

142

Lastpage

145

Abstract

Pass Gate Differential Cascode Voltage Switch (DCVS) logic has been introduced recently as a dynamic logic circuit family. Quad DCVS circuitry enhances the operability of pass gate DCVS by eliminating input signal timing constraints. Example applications are presented to demonstrate the improved performance through the use of both precharge-high and precharge-low output signals. The relative power and delay performance are presented

Keywords

delays; field effect logic circuits; logic design; timing; Quad DCVS logic; delay performance; differential cascode voltage switch logic; dynamic differential logic family; input signal timing constraints elimination; power performance; precharge-high output signals; precharge-low output signals; Adders; FETs; Logic circuits; Logic design; Logic devices; Logic gates; Robustness; Switches; Tin; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on

Conference_Location

Isla de Margarita

Print_ISBN

0-7803-4434-0

Type

conf

DOI

10.1109/ICCDCS.1998.705822

Filename

705822

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1985802