DocumentCode
1985848
Title
Revisiting shift register realization for ease of test generation and testing
Author
Toida, S.
Author_Institution
Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
fYear
1993
fDate
6-8 April 1993
Firstpage
151
Lastpage
153
Abstract
The shift register realization of sequential circuits is reexamined. Though the shift register realization requires no extra circuits for scan, and shortens test application time, it in general requires many memory elements. This paper presents a method to reduce the number of memory elements in a shift register realization.<>
Keywords
logic testing; sequential circuits; shift registers; memory elements; sequential circuits; shift register realization; test application time; test generation; Application software; Circuit faults; Circuit testing; Computer science; Feedback loop; Flip-flops; Redundancy; Sequential analysis; Sequential circuits; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313333
Filename
313333
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