DocumentCode
1985877
Title
On the design for testability of sequential circuits
Author
Sun, X. ; Lombardi, F.
Author_Institution
Texas A&M Univ., Dept. of Comput. Sci., College Station, TX, USA
fYear
1993
fDate
6-8 April 1993
Firstpage
147
Lastpage
150
Abstract
Presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) with additional circuitry such that the combinational part of the SUT and the sequential part (i.e. the flip-flops) can be tested independently (disjoint testing).<>
Keywords
design for testability; flip-flops; logic testing; sequential circuits; design for testability; disjoint testing; flip-flops; sequential circuits; system under test; Circuit testing; Combinational circuits; Controllability; Design for testability; Observability; Sequential analysis; Sequential circuits; Sun; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-8186-3830-3
Type
conf
DOI
10.1109/VTEST.1993.313334
Filename
313334
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