Testability preserving Boolean transforms for logic synthesis

Synthesis proceeds through local transformations with various objectives. If testability is a concern, these transformations are limited to those that preserve or enhance testability. Such transformations are called testability preserving transformations. The fault model used is pivotal to the analysis of any such transformation. In this paper, the authors chose single-path-propagating hazard-free robust delay fault testability to qualify them. This model was chosen because it disambiguates results of delay testing which are often inconclusive (the presence of a fault can neither be ascertained nor be denied) and ensures stuck-at fault testability as well. Unfortunately, only a few transformations are known to obey testability requirements. This limitation is a serious handicap in attaining other synthesis goals such as area and performance optimization. In this paper the authors establish a relationship between testability properties of logic transformations and their Boolean duals, the application of which enlarges the existing number of testability preserving transforms. They demonstrate further that some of the new transformations thus achieved may actually enhance testability.<>