Integration of multi-level copper metallization into a high performance sub-0.25 μm CMOS technology

Author

Venkatesan, S. ; Venkatraman, R. ; Jain, A. ; Mendonca, J. ; Anderson, S. ; Angyal, M. ; Capasso, C. ; Cope, J. ; Crabtree, P. ; Das, S. ; Farkas, J. ; Filipiak, S. ; Fiordalice, B. ; Hamilton, G. ; Herrick, M. ; Kawasaki, H. ; Islam, R. ; King, C. ; Klei

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1998

fDate

2-4 Mar 1998

Firstpage

146

Lastpage

152

Abstract

A high performance sub-0.25 μm CMOS technology has been developed with six levels of planarized copper interconnects. 0.15 μm transistors (L_gate=0.15 μm) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects to minimize wiring induced RC delays

Keywords

CMOS integrated circuits; copper; integrated circuit metallisation; 0.15 micron; 0.25 micron; 1.8 V; Cu; high performance CMOS technology; low resistance interconnects; multi-level Cu metallization; planarized Cu interconnects; reliability; six level metallisation; wiring induced RC delays minimisation; CMOS technology; Conductivity; Copper; Delay; Hot carriers; Isolation technology; MOS devices; Metallization; Temperature; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on

Conference_Location

Isla de Margarita

Print_ISBN

0-7803-4434-0

Type

conf

DOI

10.1109/ICCDCS.1998.705823

Filename

705823