• DocumentCode
    1986110
  • Title

    Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4

  • Author

    Moon, Jinyeong ; Kih, Joong Sik

  • Author_Institution
    DRAM Design Team II, Hynix Semicond. Inc., Icheon, South Korea
  • fYear
    2011
  • fDate
    15-18 May 2011
  • Firstpage
    317
  • Lastpage
    320
  • Abstract
    In this paper, a new XOR gate and architecture for parallel calculation of CRC and DBI are proposed. With this proposal, speed constraints in high-speed DRAMs such as GDDR5 and DDR4 SDRAM are relaxed. This helps minimize the latency increase and hence the effective bandwidth loss from CRC and DBI functions.
  • Keywords
    DRAM chips; logic gates; DDR4; GDDR5; XOR gate; cyclic redundancy check; data bus inversion; fast parallel CRC calculation; fast parallel DBI calculation; high-speed DDR4 SDRAM; high-speed GDDR5 SDRAM; Bandwidth; CMOS integrated circuits; Delay; Logic gates; SDRAM; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
  • Conference_Location
    Rio de Janeiro
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-9473-6
  • Electronic_ISBN
    0271-4302
  • Type

    conf

  • DOI
    10.1109/ISCAS.2011.5937565
  • Filename
    5937565
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1986110