Title :
Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4
Author :
Moon, Jinyeong ; Kih, Joong Sik
Author_Institution :
DRAM Design Team II, Hynix Semicond. Inc., Icheon, South Korea
Abstract :
In this paper, a new XOR gate and architecture for parallel calculation of CRC and DBI are proposed. With this proposal, speed constraints in high-speed DRAMs such as GDDR5 and DDR4 SDRAM are relaxed. This helps minimize the latency increase and hence the effective bandwidth loss from CRC and DBI functions.
Keywords :
DRAM chips; logic gates; DDR4; GDDR5; XOR gate; cyclic redundancy check; data bus inversion; fast parallel CRC calculation; fast parallel DBI calculation; high-speed DDR4 SDRAM; high-speed GDDR5 SDRAM; Bandwidth; CMOS integrated circuits; Delay; Logic gates; SDRAM; Transistors;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937565
