Impact of high level functional constraints on testability

When a logic module is embedded in a large circuit, the architectural level functional constraints usually cause don´t cares at the interface of this module. If the logic of the module is not synthesized using these don´t cares, then redundancy may exist making the circuit very hard to test. In this paper, architectural level circuit structural and instruction behavioral information is exploited to analyze functional constraints and extract don´t cares. The don´t cares are used to optimize the logic of the module and to remove many redundant faults.<>