Complementary structure of memristive devices based passive memory arrays

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarity written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.