Estimation of reject ratio in testing of combinatorial circuits

Author

Gaitonde, Dinesh D. ; Khare, Jitendra ; Walker, D.M.H. ; Maly, Wojciech

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1993

fDate

6-8 April 1993

Firstpage

319

Lastpage

325

Abstract

Estimating the reject ratio for integrated circuits is an important problem to a test engineer. Using information about the decrease in reject ratio with increasing test length, the test engineer can estimate the test length necessary to achieve a desired product quality goal. This paper suggests a method for estimation of reject ratio for random testing of combinatorial circuits that takes into account differing individual fault probabilities. The authors also suggest some ways of estimating the fault probabilities. They then demonstrate the method on an example and compare results to previous work.<>

Keywords

combinatorial circuits; integrated logic circuits; logic testing; production testing; combinatorial circuits; fault probabilities; integrated circuits; product quality goal; reject ratio; test length; Chromium; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Manufacturing; Predictive models; Semiconductor device modeling; Terminology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-8186-3830-3

Type

conf

DOI

10.1109/VTEST.1993.313370

Filename

313370