Title :
On parallel switch level fault simulation
Author :
Ryan, C.A. ; Tront, J.G.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<>
Keywords :
CMOS integrated circuits; computational complexity; digital simulation; logic CAD; many-valued logics; parallel processing; hardware accelerated fault simulator; many-valued logic; parallel processing; parallel switch level fault simulation; reverse level ordering; switch level circuit partitioning; Acceleration; Circuit faults; Circuit simulation; Computational modeling; Degradation; Hardware; Logic; Parallel processing; Switches; Switching circuits;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313375
