Title :
Sensitivity analysis of a radiation immune CMOS logic family under defect conditions
Author :
Ingermann, E.H. ; Frenzel, J.F.
Author_Institution :
Dept. of Electr. Eng., Idaho Univ., Moscow, ID, USA
Abstract :
Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>
Keywords :
CMOS integrated circuits; integrated logic circuits; radiation hardening (electronics); sensitivity analysis; defect conditions; radiation immune CMOS logic family; resistive shorts; sensitivity analysis; single event upset; transition delay; CMOS logic circuits; CMOS process; CMOS technology; Circuit faults; Delay; Semiconductor device modeling; Sensitivity analysis; Space technology; Virtual manufacturing; Voltage;
Conference_Titel :
VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-8186-3830-3
DOI :
10.1109/VTEST.1993.313378
