A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance

Author

Satoh, S. ; Hagiwara, H. ; Tanzawa, T. ; Takeuchi, K. ; Shirota, R.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1997

fDate

10-10 Dec. 1997

Firstpage

291

Lastpage

294

Abstract

This paper describes the key technology to realize a scaled NAND EEPROM with the minimized program disturbance. It has been clarified for the first time that the program disturbance caused by neighboring cells is drastically improved by reducing the field implantation dose. The limitation of conventional LOGOS width is estimated to be about 0.56 /spl mu/m. Moreover, a careful device design and an optimization of the bottom implantation are essential in an advanced STI cell.

Keywords

EPROM; MOS memory circuits; NAND circuits; circuit optimisation; integrated memory circuits; ion implantation; isolation technology; 0.56 micron; LOGOS width; NAND EEPROMs; advanced STI cell; bottom implantation optimisation; field implantation dose; isolation-scaling technology; minimized program disturbance; Carbon capture and storage; Design optimization; EPROM; Equivalent circuits; Isolation technology; Laboratories; Leakage current; Microelectronics; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-4100-7

Type

conf

DOI

10.1109/IEDM.1997.650384

Filename

650384