Blind sampling clock adjustment in OFDM power line commmunication

OFDM modulation technique has been recently considered for high bit rate powerline communication (PLC) due to robustness against multipath frequency selective fading, impulsive and narrowband noise as well as simple spectrum shaping and low-complexity implementation. Sampling clock offset caused by non-synchronized analogue to digital converter(ADC) is one of the major problems that affects each OFDM systems severely. In this paper, a new clock offset timing recovery approach based on symmetrical spectrum of PLC is proposed. In this method, redundant information in OFDM sub-channel which are discarded after FFT demodulation is used to timing error (TE) estimation. The performance of algorithm has been evaluated on a typical PLC channel through computer simulations.