DocumentCode
1986731
Title
Spurs suppression and deterministic jitter correction in all-digital frequency synthesizers, current state and future directions
Author
Sotiriadis, Paul P.
Author_Institution
Sotekco Electron. LLC, USA
fYear
2011
fDate
15-18 May 2011
Firstpage
422
Lastpage
425
Abstract
All-digital frequency synthesizers are favored by modern nano-scale CMOS technologies but suffer from strong frequency spurs and timing irregularities. This paper reviews the time-domain-correction and spurs-suppression techniques for all-digital frequency synthesizers, identifies their strengths and weaknesses and provides new research directions.
Keywords
CMOS integrated circuits; frequency synthesizers; interference suppression; jitter; all-digital frequency synthesizer; deterministic jitter correction; nanoscale CMOS technology; spurs suppression; time-domain-correction; Adders; Clocks; Delay; Frequency synthesizers; Patents; Phase locked loops; Synthesizers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location
Rio de Janeiro
ISSN
0271-4302
Print_ISBN
978-1-4244-9473-6
Electronic_ISBN
0271-4302
Type
conf
DOI
10.1109/ISCAS.2011.5937592
Filename
5937592
Link To Document